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STMPE801
8-bit port expander Xpander logic
Features

8 GPIO Operating voltage 1.65V - 3.6V I/O voltage 1.65V-3.6V Interrupt output pin Reset input pin Wake up feature on each I/O Up to 2 devices sharing the same bus (1 address line) <1A suspend current SO-16 QFN16L
Application

Portable media player, Game console Mobile phone, Smart phone
Description
The STMPE801 is a GPIO (General Purpose Input / Output) port expander able to interface a main digital ASIC via the two-line bidirectional bus (I2C); separate GPIO Expander IC is often used in Mobile-Multimedia platforms to solve the problems of the limited amounts of GPIOs usually available on the Digital Engine. The STMPE801 offers great flexibility as each I/Os is configurable as input, output. This device has been designed very low quiescent current, and includes wake up feature for each I/O, to optimize the power consumption of the IC.
Table 1. Device summary
Order codes STMPE801QTR STMPE801MTR Package QFN16L (2.6mm x 1.8mm) SO-16 Packaging Tape and reel (3000 per reel) Tape and reel (2500 per reel)
July 2007
Rev 4
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www.st.com 26
Contents
STMPE801
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
I2C module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 I2C address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledgement in read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Turning I2C block OFF and ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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STMPE801
Contents
7
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 7.2 System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 System control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8
Interrupt, power supply & reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.1 8.2 8.3 8.4 8.5 Interrupt enable GPIO mask register (IEGPIOR) . . . . . . . . . . . . . . . . . . . 16 Interrupt status GPIO register (ISGPIOR) . . . . . . . . . . . . . . . . . . . . . . . . 17 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Block diagram
STMPE801
1
Block diagram
Figure 1. Block diagram
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STMPE801
Pin settings
2
2.1
Pin settings
Pin connection
Figure 2. Pin connection
QFN16L
1 2 3 4
16 15 14 13
Top View
5 6 7 8 12 11 10 9
SO-16
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Pin settings
STMPE801
2.2
Pin assignment
Table 2. Pin assignment
Pin N Name SO-16 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 QFN16L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INT Reset CLOCK Address DATA VCC VIO GND GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 INT output Reset Input (Active Low) I2C Clock I2C Address I2C Data Supply voltage for I2C block Supply voltage for GPO and GPIO Controller (Note: VIO must be VCC) GND GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 Function
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STMPE801
Maximum rating
3
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
3.1
Absolute maximum rating
Table 3. Absolute maximum rating
Symbol VCC VIO VESD (HBM) Supply voltage GPO supply voltage ESD protection on each GPO pin Parameter Value 4.5 4.5 2 Unit V V KV
3.2
Thermal data
Table 4. Thermal data
Value Symbol TA TSTG Parameter Min Operating ambient temperature Operating storage temperature -40 -65 Typ Max +85 155 C C/W Unit
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Electrical specification
STMPE801
4
4.1
Electrical specification
DC electrical characteristics
Table 5. DC electrical characteristics
Value Symbol VCC VIO Ipd Icc Max Icc Normal Parameter Core supply voltage IO suppli voltage Power down current Operating current (No peripheral activity) Operating current (No peripheral activity) I2C running at 400KHz 100% traffic density I2C running at 400KHz 1% traffic density No I2C activity VIO = 1.8-3.3V VIO = 1.8-3.3V -0.3V 0.70VIO -0.3V 0.75VIO -0.3V 0.75Vc c 0.2 10 0.5 Test conditions Min 1.65 1.65 Typ Max 3.6 3.6 1 0.5 15 1 0.30VIO VIO+0.3V 0.25VIO VIO+0.3V 0.25VCC VCC+0.3V V V A mA A A V V V V V V Unit
ICC Operating current Suspend (No peripheral activity) VIL VIH VOL VOH Input voltage low state Input voltage high state
Output voltage low state VIO = 1.8-3.3V, IOL=8mA Output voltage high state VIO=1.8-3.3V, IOL=8mA
VOL (I2C) Output voltage low state Vcc=1.8-3.3V, IOL=8mA VOH (I2C) Output voltage high state Vcc=1.8-3.3V, IOL=8mA
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STMPE801
I2C module
5
I2C module
STMPE801 is interface to the main processor using an I2C bus.
5.1
I2C address
Addressing scheme of STMPE801 is designed to allow up to 2 devices to be connected to the same I2C bus. Figure 3. Addressing scheme
Table 6. Addresses
ADDR0 0 1 Address 0x82 0x88 Note
For the bus master to communicate to the slave device, the bus master must initiate a Start condition anf followed by the slave device address. Accompanying the slave device address, there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for write operation. If a match occurs on the slave device address, the corresponding device gives an acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction.
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I2C module Figure 4. I2C timing
STMPE801
Table 7. I2C address
Symbol fSCL tLOW tHIGH tF tHD:STA tSU:STA tSU:DAT tHD:DAT tSU:STO tBUF Parameter SCL clock frequency Clock low period Clock high period SDA and SCL fall time START condition hold time (After this period the first clock is generated) START condition setup time (Only relevant for a repeated start period) Data setup time Data hold time STOP condition setup time Time the bust must be free before a new trasmission can start 600 600 100 0 600 1.3 Min 0 1.3 600 300 Typ Max 400 Unit kHz s ns ns ns ns ns s ns s
5.2
I2C features
The features that are supported by the I2C interface are as below:

I2C slave device Operates at 1.8V Compliant to Philips I2C specification version 2.1 Supports standard (uo to 100Kbps) and fast (up to 400Kbps) modes
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STMPE801
I2C module
5.3
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and will not respond to any transaction unless one is encountered.
5.4
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A Stop condition terminates communication between the slave device and bus master. A read command that is followed by NoAck can be followed by a Stop condition to force the slave device into idle mode. When the slave device is in idle mode, it is ready to receive the next I2C transaction. A Stop condition at the end of a write command stops the write operation to registers.
5.5
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDATA in high state if it would to not acknowledge the receipt of the data.
5.6
Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA signal must be stable during the rising edge of SCLK and the SDATA signal must change only when SCLK is driven low.
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I2C module
STMPE801
5.7
Operation modes
Table 8. Operation modes
Mode Bytes Programming Sequence START, Device Address, R/W = 0, Register Address to be read RESTART, Device Address, R/W = 1, Data Read, STOP 1 If no STOP is issued, the Data Read can be continuously preformed. If the register address falls within the range that allows address autoincrement, then register address auto-increments internally after every byte of data being read. For register address that falls within a nonincremental address range, the address will be kept static throughout the entire read operations. Refer to the Memory Map table for the address ranges that are auto and non-increment. START, Device Address, R/W = 0, Register Address to be written, Data Write, STOP If no STOP is issued, the Data Write can be continuously performed. If the register address falls within the range that allows address autoincrement, then register address auto-increments internally after every byte of data being written in. For register address that falls within a nonincremental address range, the address will be kept static throughout the entire write operations. Refer to the Memory Map table for the address ranges that are auto and non-increment.
Read
Write
1
Figure 5.
One Byte Read More than One Byte Read
Read and write modes (random and sequential)
RnW=0 Ack RnW=1 Ack reStart Dev Addr Reg Addr Dev Addr Data Read NoAck Stop Start
RnW=0 Ack
Ack
RnW=1 Ack
reStart
Dev Addr
Reg Addr
Dev Addr
Data Read
Data Read + 1
Data Read + 2
One Byte Write More than One Byte Write
Dev Addr
Reg Addr
Data to be Written
RnW=0 Ack
Start
Dev Addr
RnW=0 Ack
Reg Addr
Data to Write
Ack Stop
Ack
Data to Write + 1
Data to Write + 2
Start
Master Slave
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Ack Stop
Ack
Ack
Ack
NoAck Stop
Start
Ack
Ack
Ack
STMPE801
I2C module
5.8
Read operation
A write is first performed to load the register address into the Address Counter but without sending a Stop condition. Then, the bus master sends a reStart condition and repeats the Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the content of the addressed byte. If no more data is to be read, the bus master must not acknowledge the byte and terminates the transfer with a Stop condition. If the bus master acknowledges the data byte, then it can continue to perform the data reading. To terminate the stream of data byte, the bus master must not acknowledge the last output byte and follow by a Stop condition. If the address of the register written into the Address Counter falls within the range of addresses that has the auto-increment function, the data being read will be coming from consecutive addresses, with the internal Address Counter automatically increments after each byte output. After the last memory address, the Address Counter 'rolls-over' and the device continue to output data from the memory address of 0x00. Similarly, for the address of register that falls within non-increment range of addresses, the output data byte comes from the same address (which is the address pointed by the Address Counter).
5.9
Acknowledgement in read operation
For the above read command, the slave device waits, after each byte read, for an acknowledgement during the ninth bit time. If the bus master does not drive the SDA to low state, then the slave device terminates and switches back to its idle mode, waiting for the next command.
5.10
Write operations
A write is first performed to load the register address into the Address Counter without sending a Stop condition. After the bus master receives an acknowledgement from the slave device, it may start to send a data byte to the register (pointed by the Address Counter). The slave device again acknowledges and the bus master terminates the transfer with a Stop condition. If the bus master would like to continue to write more data, it can just continue write operation without issuing the Stop condition. Whether the Address Counter autoincrements or not after each data byte write, depends on the address of the register written into the Address Counter. After the bus master writes the last data byte and the slave device acknowledges the receipt of the last data, the bus master may terminates the write operation by sending a Stop condition. When the Address Counter reaches the last memory address, it 'rolls-over' on the next data byte write.
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Turning I2C block OFF and ON
STMPE801
5.11
General call
A general call address is a transaction with the slave address of 0x00 and R/W = 0. When a general call address is made, the device responds to this transaction with an acknowledgement and behaves as a slave-receiver mode. The meaning of a general call address is defined in the second byte sent by the master-transmitter. Table 9. General call
R/W 0 Second Byte Value 0x06 Definition 2-byte transaction in which the second byte tells the slave device to reset and write (or latch in) the 1-bit programmable part of the slave address. 2-byte transaction in which the second byte tells the slave device not to reset and write (or latch in) the 1-bit programmable part of the slave address. Not allowed as second byte.
0
0x04
0
0x00
Note:
All other second byte value will be ignored.
6
Turning I2C block OFF and ON
STMPE801 operates entirely on the I2C clock. When there are no activity on the I2C bus, current consumption of the device is extremely low. However, when there are activity on the I2C bus, current consumption increases, even if the I2C traffic is not directed to the assigned address. Host system may choose to shut-down the I2C block in the STMPE801, if no access to the registers are required. This feature allows the current consumption to drop to the minimum. Host system turns OFF the I2C block by writing `1' into the I2C_SHDN bit. The I2C block will shut down on the next valid clock edge of the I2C clock signal. In this state, the device CANNOT be accessed by I2C, as the I2C has shut down completely. To turn ON the I2C block, system host must reset the STMPE801 in order to re-activate the I2C block. This could be done by hardware assertion of the RESET pin.
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STMPE801
Register map
7
Register map
Table 10. Register map
Address 0x00 0x02 0x04 0x08 0x09 0x10 0x11 0x12 Register Name Chip ID Version ID SystemControl IEGPIOR ISGPIOR GPMR GPSR GPDR Size (bit) 16 8 8 8 8 8 8 8 0x0801 Revision number Reset and interrupt control GPIO interrupt enable register GPIO interrupt status register GPIO monitor pin state register GPIO set pin state register GPIO set pin direction register Function
7.1
System and identification registers
Table 11. System and identification registers
Register name Chip ID Version ID Size (bit) 16 8 0x0801 Revision number: 0x01 (Engineering) 0x02 (Final silicon) Function
Systemcontrol
8
7.2
System control register
Table 12. System control register
Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 INTPolarity `1' for active HI, `0' for active LOW INT_Enable `1' to enable, `0' to disable INT output Name SoftReset I2C_SHDN Description Writing `1' to this bit causes a soft reset Writing `1' to this bit shuts down the I2C block on the next valid I2C clock.
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Interrupt, power supply & reset
STMPE801
8
Interrupt, power supply & reset
STMPE801 could be configured to generate an interrupt when there is a logic transition of any of the GPIO configured as input.
8.1
Interrupt enable GPIO mask register (IEGPIOR)
IEGPIOR register is used to enable the interruption from a particular GPIO interrupt source to the host. The IEG[7:0] bits are the interrupt enable mask bits correspond to the GPIO[7:0] pins.
IEGPIOR Bit 7 IEG7 R/W Reset Value RW 0 6 IEG6 RW 0 5 IEG5 RW 0 4 IEG4 RW 0 3 IEG3 RW 0 2 IEG2 RW 0 1 IEG1 RW 0 0 IEG0 RW 0
Table 13. Register
Bits 7:0 Name IEG[x] Description Interrupt Enable GPIO Mask (where x = 7 to 0) Writing a `1' to the IE[x] bit will enable the interruption to the host.
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STMPE801
Interrupt, power supply & reset
8.2
Interrupt status GPIO register (ISGPIOR)
ISGPIOR register monitors the status of the interruption from a particular GPIO pin interrupt source to the host. Regardless whether the IEGPIOR bits are enabled or not, the ISGPIOR bits are still updated. The ISG[9:0] bits are the interrupt status bits correspond to the GPIO[7:0] pins.
ISGPIOR Bit 7 ISG7 R/W Reset Value RW 0 6 ISG6 RW 0 5 ISG5 RW 0 4 ISG4 RW 0 3 ISG3 RW 0 2 ISG2 RW 0 1 ISG1 RW 0 0 ISG0 RW 0
Table 14. Register
Bits Name Description Interrupt Status GPIO (where x = 7 to 0) Read: Interrupt Status of the GPIO[x]. Reading the register will clear any bits that has been set to `1' Write: Writing to this register has no effects
7:0
ISG[x]
8.3
GPIO controller
A total of 8 GPIOs are available in the STMPE801 port expander IC. The GPIO controller contains the registers that allow the host system to configure each of the pins as input or output. Unused GPIOs should be configured as outputs to minimize the power consumption. A group of registers are used to control the exact function of each of the 8 GPIO. The registers and their respective address is listed in the following table. Table 15. Register
Address 0x10 0x11 0x12 Register Name GPMR GPSR GPDR Description GPIO monitor pin state register GPIO set pin state register GPIO set pin direction register Auto-Increment (during sequential R/W) Yes Yes Yes
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Interrupt, power supply & reset All GPIO registers are named as GPxx, where Xxx represents the functional group
STMPE801
Bit GPxx
7 IO-7
6 IO-6
5 IO-5
4 IO-4
3 IO-3
2 IO-2
1 IO-1
0 IO-0
The function of each bit is shown in the following table: Table 16. Pin function
Register Name GPIO Monitor Pin State GPIO Set Pin State GPIO Set Pin Direction Function Reading this bit yields the current state of the bit. Writing has no effect. Writing `1' to this bit causes the corresponding GPIO to go to `1' state. Writing `0' to this bit causes the corresponding GPIO to go to `0' state. `0' sets the corresponding GPIO to input state, and `1' sets it to output state. All bits are `0' on reset.
On power-up reset, all GPIO are set as input.
8.4
Power supply
STMPE801 GPIO operates from a separate supply pin (VIO). This dedicated supply pin provides a level-shifting feature to the STMPE801. GPIO will remain valid until VIO is removed. The host system may choose to turn off VCC supply while keeping VIO supplied. However it is not allowed to turn off supply to VIO, while keeping the Vcc supplied.
8.5
Reset
STMPE801 is equipped with an internal POR circuit that holds the device in reset state, until the VIO supply input is valid. The internal POR is tied to the Vio supply pin. The reset pin allows the host to reset the STMPE801 directly. Minimum pulse width of reset signal is 100s. During the period when reset pin is asserted, all GPIO default to inputs.
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STMPE801
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data Table 17. QFN16L mechanical data
mm. Dim. Min A A1 b D E e L 0.35 0.15 2.50 1.70 0.45 Typ 0.55 0.02 0.20 2.60 1.80 0.40 0.40 0.45 0.014 Max 0.60 0.05 0.25 2.70 1.90 0.006 0.098 0.067 Min 0.020 Typ 0.022 0.001 0.008 0.102 0.071 0.016 0.016 inch
STMPE801
Max 0.024 0.002 0.010 0.106 0.075
0.018
Figure 6.
Package dimensions
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STMPE801 Figure 7. Footprint recommendation
Package mechanical data
Figure 8.
Marking
A
B
A: Device Marking (525) B: Dot
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Package mechanical data Figure 9. QFN16L tape and reel information
STMPE801
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STMPE801 Figure 10. QFN16L tape and reel information (continued)
Package mechanical data
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Package mechanical data
STMPE801
Table 18. SO-16 mechanical data
mm. Dim. Min. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 Typ Max. 1.75 0.25 1.64 0.46 0.25 0.013 0.007 0.019 0.004 Min. Typ. Max. 0.068 0.010 0.063 0.018 0.010 inch
Figure 11. Package dimensions
0016020D
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STMPE801
Revision history
10
Revision history
Table 19. Revision history
Date 07-Dec-2006 22-Jan-2007 27-Apr-2007 02-Jul-2007 Revision 1 2 3 4 Initial release Added Marking and Reel information Updated Chapter 8.4 and Chapter 8.5 on page 18 Coverpage QFN package drawing updated Changes
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STMPE801
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